The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Sep. 12, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yen-Cheng Liu, Portland, OR (US);

Aamer Jaleel, Northborough, MA (US);

Bongjin Jung, Westford, MA (US);

Zeshan A. Chishti, Hillsboro, OR (US);

Adrian C. Moga, Portland, OR (US);

Eric Delano, Fort Collins, CO (US);

Ren Wang, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 12/084 (2016.01); G06F 12/0811 (2016.01); G06F 12/0842 (2016.01); G06F 12/0846 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0842 (2013.01); G06F 12/0846 (2013.01); G06F 12/0831 (2013.01); G06F 2212/1024 (2013.01);
Abstract

In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.


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