The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2017
Filed:
Jul. 22, 2016
Jang-gn Yun, Hwaseong-si, KR;
Zhiliang Xia, Hwaseong-si, KR;
Ahn-sik Moon, Hwaseong-si, KR;
Se-jun Park, Hwaseong-si, KR;
Joon-sung Lim, Yongin-si, KR;
Sung-min Hwang, Seoul, KR;
Jang-Gn Yun, Hwaseong-si, KR;
Zhiliang Xia, Hwaseong-si, KR;
Ahn-Sik Moon, Hwaseong-si, KR;
Se-Jun Park, Hwaseong-si, KR;
Joon-Sung Lim, Yongin-si, KR;
Sung-Min Hwang, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.