The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Sep. 21, 2015
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Chen-Yueh Kung, New Taipei, TW;

Hsin-I Chuang, New Taipei, TW;

Ting-You Wei, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/14 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17 (2013.01); H01L 2924/1511 (2013.01); H01L 2924/15311 (2013.01);
Abstract

The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces.


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