The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Jun. 01, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventor:

Weng Foong Yap, Chandler, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4846 (2013.01); H01L 21/481 (2013.01); H01L 21/568 (2013.01); H01L 23/49805 (2013.01); H01L 23/49838 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 25/105 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/13008 (2013.01); H01L 2224/13024 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A semiconductor device package and method of manufacturing is provided. An interconnect pre-assembly includes a first frame having a plurality of first signal conduits affixed to a second frame having a plurality of second signal conduits embedded in a second substrate forming an electrical coupling between one or more first signal conduits and one or more of the second signal conduits. One or more conductive balls are connected to the one or more second signal conduits. The interconnect pre-assembly is placed over a semiconductor die, having at least one of the first conductive balls disposed over the semiconductor die. An encapsulant encapsulates the interconnect pre-assembly, the semiconductor die, and the one or more conductive balls, such that a portion of the one or more first conductive balls is exposed at a top surface of the encapsulant.


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