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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9780205 B1

PDFFull Text
Expired
Date of Patent:
Oct. 03, 2017

Filed:

Aug. 04, 2014

Insulated gate type semiconductor device having floating regions at bottom of trenches in cell region and circumferential region and manufacturing method thereof

Applicants:

Jun Saito, Nagoya, JP;

Hirokazu Fujiwara, Miyoshi, JP;

Tomoharu Ikeda, Nisshin, JP;

Yukihiko Watanabe, Nagoya, JP;

Toshimasa Yamamoto, Ichinomiya, JP;

Inventors:

Jun Saito, Nagoya, JP;

Hirokazu Fujiwara, Miyoshi, JP;

Tomoharu Ikeda, Nisshin, JP;

Yukihiko Watanabe, Nagoya, JP;

Toshimasa Yamamoto, Ichinomiya, JP;

Assignees:

TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota, JP;

DENSO CORPORATION, Kariya, JP;

Attorney:

Oliff PLC

Primary Examiner:

Michael Jung

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/761 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 21/761 (2013.01); H01L 29/0623 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01); H01L 21/046 (2013.01);
Abstract

A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

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Saito, Jun. (2017). Insulated gate type semiconductor device having floating regions at bottom of trenches in cell region and circumferential region and manufacturing method thereof (U.S. Patent No. 9780205). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9780205

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