The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Oct. 18, 2012
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Purdue Research Foundation, West Lafayette, IN (US);

Inventors:

Peide Ye, West Lafayette, IN (US);

Zhiyuan Cheng, Lincoln, MA (US);

Yi Xuan, West Lafayette, IN (US);

Yanqing Wu, West Lafayette, IN (US);

Bunmi Adekore, Medford, MA (US);

James Fiorenza, Wilmington, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66522 (2013.01); H01L 21/02299 (2013.01); H01L 21/02301 (2013.01); H01L 21/02392 (2013.01); H01L 21/28264 (2013.01); H01L 29/517 (2013.01); H01L 29/66446 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01);
Abstract

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.


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