The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2017
Filed:
Jul. 07, 2016
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Kensuke Ota, Tama, JP;
Toshifumi Irisawa, Bunkyo, JP;
Tomoya Kawai, Kawasaki, JP;
Daisuke Matsushita, Fujisawa, JP;
Tsutomu Tezuka, Tsukuba, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/24 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); G11C 16/10 (2006.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); G11C 5/025 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 29/24 (2013.01);
Abstract
A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.