The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Dec. 20, 2013
Applicants:

Darrell G. Hill, Tempe, AZ (US);

Marcel N. Tutt, Scottsdale, AZ (US);

Inventors:

Darrell G. Hill, Tempe, AZ (US);

Marcel N. Tutt, Scottsdale, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 23/482 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/735 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 23/481 (2013.01); H01L 23/4824 (2013.01); H01L 29/4175 (2013.01); H01L 29/41708 (2013.01); H01L 29/42304 (2013.01); H01L 29/735 (2013.01); H01L 29/7786 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/41758 (2013.01); H01L 29/7816 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.


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