The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Dec. 23, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Das Sharma, Saratoga, CA (US);

Daniel S. Froelich, Portland, OR (US);

Venkatraman Iyer, Austin, TX (US);

Michelle C. Jen, Sunnyvale, CA (US);

Rahul R. Shah, Marlborough, MA (US);

Eric M. Lee, Fort Collins, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/385 (2013.01); G06F 13/4282 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01);
Abstract

An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.


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