The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Jul. 25, 2013
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Nobuo Fujiwara, Tokyo, JP;

Yasuhiro Kagawa, Tokyo, JP;

Rina Tanaka, Tokyo, JP;

Yutaka Fukui, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 31/028 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 21/0475 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 29/0696 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/66068 (2013.01); H01L 29/66666 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 21/046 (2013.01); H01L 21/049 (2013.01);
Abstract

A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.


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