The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2017
Filed:
Jul. 09, 2015
Kabushiki Kaisha Toyota Jidoshokki, Kariya-shi, Aichi-ken, JP;
Sicoxs Corporation, Tokyo, JP;
Ko Imaoka, Kariya, JP;
Motoki Kobayashi, Tokyo, JP;
Hidetsugu Uchida, Tokyo, JP;
Kuniaki Yagi, Tokyo, JP;
Takamitsu Kawahara, Tokyo, JP;
Naoki Hatta, Tokyo, JP;
Akiyuki Minami, Tokyo, JP;
Toyokazu Sakata, Tokyo, JP;
Tomoatsu Makino, Tokyo, JP;
Mitsuharu Kato, Tokyo, JP;
KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, Kariya-shi, Aichi, JP;
SICOXS CORPORATION, Chiyoda-ku, Tokyo, JP;
Abstract
A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.