The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Jan. 07, 2016
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Yung-Hui Wang, Kaohsiung, TW;

Ying-Te Ou, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H05K 1/185 (2013.01); H05K 1/188 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15153 (2013.01); H05K 3/429 (2013.01); H05K 3/4602 (2013.01); H05K 3/4652 (2013.01); H05K 2201/09536 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/063 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49204 (2015.01); Y10T 29/49213 (2015.01);
Abstract

An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.


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