The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9767247 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 19, 2017

Filed:

Jul. 13, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ruibing Lu, Santa Clara, CA (US);

Sabyasachi Das, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5045 (2013.01);
Abstract

A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the processor, the second look-up table structure and routing, using the processor, the second look-up table structure.


Find Patent Forward Citations

Lu, Ruibing. (2017). Look-up table restructuring for timing closure in circuit designs (U.S. Patent No. 9767247). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9767247

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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