The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Oct. 02, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Xusheng Wu, Hopewell Junction, NY (US);

Bingwu Liu, Ballston Spa, NY (US);

Randy Mann, Milton, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/265 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 21/823431 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01);
Abstract

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.


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