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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9761546 B1

PDFFull Text
Date of Patent:
Sep. 12, 2017

Filed:

Feb. 23, 2016

Trap layer substrate stacking technique to improve performance for rf devices

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Yu Cheng, Tainan, TW;

Chih-Ping Chao, Juhdong Township, TW;

Kuan-Chi Tsai, Kaohsiung, TW;

Shih-Shiung Chen, Tainan, TW;

Wei-Kung Tsai, Tainan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Amar Movva

Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/28 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/28008 (2013.01); H01L 21/6835 (2013.01); H01L 21/76251 (2013.01); H01L 21/76877 (2013.01); H01L 21/84 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 27/1211 (2013.01); H01L 29/1079 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/05025 (2013.01);
Abstract

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

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