The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2017
Filed:
Oct. 16, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Raghunandan Chaware, Sunnyvale, CA (US);
Amitava Majumdar, San Jose, CA (US);
Glenn O'Rourke, Gilroy, CA (US);
Inderjit Singh, Saratoga, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/152 (2013.01); H01L 2924/153 (2013.01); H01L 2924/1515 (2013.01);
Abstract
Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.