The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Dec. 29, 2015
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Kuei-Sheng Wu, Miaoli County, TW;

Ming-Tse Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76829 (2013.01); H01L 21/76841 (2013.01); H01L 21/76898 (2013.01); H01L 23/49827 (2013.01); H01L 23/53238 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD layer on a substrate and a buffer layer on the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.


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