The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Jul. 16, 2015
Applicant:

Super Group Semiconductor Co., Ltd., New Taipei, TW;

Inventors:

Yuan-Ming Lee, Taichung, TW;

Chun-Ying Yeh, Hisnchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/407 (2013.01); H01L 21/0217 (2013.01); H01L 29/063 (2013.01); H01L 29/0607 (2013.01); H01L 29/0611 (2013.01); H01L 29/165 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 29/66727 (2013.01);
Abstract

A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.


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