The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Dec. 28, 2012
Applicant:

Nepes Co., Ltd., Eumseong-gun, Chungcheongbuk-do, KR;

Inventors:

Yong-Tae Kwon, Suwon-si, KR;

Jun-Kyu Lee, Chungcheongbuk-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/565 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24 (2013.01); H01L 2224/82 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01);
Abstract

Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.


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