The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Jul. 13, 2015
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Ji-Gang Pan, Beijing, CN;

Han-Chuan Fang, Singapore, SG;

Boon-Tiong Neo, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01); H01L 27/11531 (2017.01); H01L 27/11541 (2017.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 21/3212 (2013.01); H01L 21/32056 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 27/11531 (2013.01); H01L 27/11541 (2013.01);
Abstract

A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.


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