The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Dec. 09, 2016
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chih Kai Yang, Kaohsiung, TW;

Chen Yu Cheng, Taipei, TW;

Shih Chin Lee, Taichung, TW;

Ching Hung Wang, Hsinchu, TW;

Tzung-Ting Han, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/06 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 27/11521 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension, in which each memory cell of the multiple memory cells includes a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, and a first electrode layer on the tunnel dielectric layer. Along the first dimension, the channel region of each memory cell of the multiple memory cells is separated from the channel region of an adjacent memory cell of the multiple memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate up to an inter-electrode dielectric layer.


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