The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Sep. 15, 2014
Applicant:

Advanced Semiconductor Engineering, Inc., Kaosiung, TW;

Inventors:

Jen-Kuang Fang, Kaohsiung, TW;

Kuo-Hua Chen, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 24/33 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/06164 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/13664 (2013.01); H01L 2924/381 (2013.01);
Abstract

The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.


Find Patent Forward Citations

Loading…