The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Jul. 13, 2015
Synopsys, Inc., Mountain View, CA (US);
Yi-Min Jiang, San Jose, CA (US);
Xiang Qui, Mountain View, CA (US);
Balkrishna R. Rashingkar, San Jose, CA (US);
Yan Lin, Pleasanton, CA (US);
SYNOPSYS, INC., Mountain View, CA (US);
Abstract
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.