The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2017
Filed:
Apr. 29, 2015
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/131 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73153 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/10253 (2013.01);
Abstract
Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.