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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9735154 B1

PDFFull Text
Date of Patent:
Aug. 15, 2017

Filed:

Oct. 20, 2015

Semiconductor structure having gap fill dielectric layer disposed between fins

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Andy Chih-Hung Wei, Queensbury, NY (US);

Dae-han Choi, Loudonville, NY (US);

Dae Geun Yang, Watervliet, NY (US);

Xiang Hu, Clifton Park, NY (US);

Mariappan Hariharaputhiran, Ballston Lake, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:

Williams Morgan, P.C.

Primary Examiner:

Stephen W Smoot

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/033 (2006.01); H01L 21/475 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02271 (2013.01); H01L 21/0332 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/475 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

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