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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9735092 B1

PDFFull Text
Date of Patent:
Aug. 15, 2017

Filed:

Jun. 20, 2016

Manufacturing method of chip package structure

Applicant:

Chipmos Technologies Inc., Hsinchu, TW;

Inventors:

Yu-Tang Pan, Hsinchu, TW;

Shih-Wen Chou, Hsinchu, TW;

Assignee:

ChipMOS Technologies Inc., Hsinchu, TW;

Attorney:

Jianq Chyun IP Office

Primary Examiner:

Moazzam Hossain

Assistant Examiner:

Farun Lu

Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49568 (2013.01); H01L 21/4828 (2013.01); H01L 21/4871 (2013.01); H01L 21/4875 (2013.01); H01L 21/56 (2013.01); H01L 23/3114 (2013.01); H01L 23/3736 (2013.01); H01L 23/49503 (2013.01); H01L 23/49524 (2013.01); H01L 23/49541 (2013.01); H01L 23/49861 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 23/3107 (2013.01); H01L 23/49586 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/181 (2013.01);
Abstract

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

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