The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Jul. 15, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Hsing-Lien Lin, Hsinchu, TW;

Chia-Shiung Tsai, Hsinchu, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Huey-Chi Chu, Hsinchu, TW;

Hai-Dang Trinh, Hsinchu, TW;

Wen-Chuan Chiang, Hsinchu, TW;

Wei-Min Tseng, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/0226 (2013.01); H01L 23/5223 (2013.01);
Abstract

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.


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