The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Jul. 16, 2012
Applicants:

Sambo He, Riverside, CA (US);

W. Eric Boyd, Long Beach, CA (US);

Inventors:

Sambo He, Riverside, CA (US);

W. Eric Boyd, Long Beach, CA (US);

Assignee:

PFG IP LLC, Tiburon, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H05K 1/0275 (2013.01); H05K 3/4602 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/30107 (2013.01); H05K 1/186 (2013.01); H05K 3/4647 (2013.01);
Abstract

A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.


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