The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2017
Filed:
Sep. 07, 2011
Abraham F. Yee, Cupertino, CA (US);
Joe Greco, San Jose, CA (US);
Jun Zhai, San Jose, CA (US);
Joseph Minacapelli, Sunnyvale, CA (US);
John Y. Chen, Cupertino, CA (US);
Abraham F. Yee, Cupertino, CA (US);
Joe Greco, San Jose, CA (US);
Jun Zhai, San Jose, CA (US);
Joseph Minacapelli, Sunnyvale, CA (US);
John Y. Chen, Cupertino, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.