The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9728395 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 08, 2017

Filed:

Sep. 28, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Helmut Oefner, Zorneding, DE;

Nico Caspary, München, DE;

Mohammad Momeni, Villach, AT;

Reinhard Ploss, Unterhaching, DE;

Francisco Javier Santos Rodriguez, Villach, AT;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/268 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 21/18 (2006.01); H01L 21/225 (2006.01); H01L 21/28 (2006.01); H01L 21/322 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02008 (2013.01); H01L 21/0201 (2013.01); H01L 21/02002 (2013.01); H01L 21/02005 (2013.01); H01L 21/02016 (2013.01); H01L 21/268 (2013.01); H01L 21/324 (2013.01); H01L 29/66348 (2013.01); H01L 21/187 (2013.01); H01L 21/2257 (2013.01); H01L 21/28238 (2013.01); H01L 21/3221 (2013.01); H01L 21/3242 (2013.01);
Abstract

A method for manufacturing a substrate waferincludes providing a device wafer () having a first side () and a second side (); subjecting the device wafer () to a first high temperature process for reducing the oxygen content of the device wafer () at least in a region () at the second side (); bonding the second side () of the device wafer () to a first side () of a carrier wafer () to form a substrate wafer (); processing the first side () of the substrate wafer () to reduce the thickness of the device wafer (); subjecting the substrate wafer () to a second high temperature process for reducing the oxygen content at least of the device wafer (); and at least partially integrating at least one semiconductor component () into the device wafer () after the second high temperature process.


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