The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Sep. 26, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rahul Pal, Bangalore, IN;

Ishwar Agarwal, Hillsboro, OR (US);

Yen-Cheng Liu, Portland, OR (US);

Joseph Nuzman, Haifa, IL;

Ashok Jagannathan, Bangalore, IN;

Bahaa Fahim, San Jose, CA (US);

Nithiyanandan Bashyam, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0875 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 12/0831 (2013.01); G06F 2212/452 (2013.01);
Abstract

An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache ('MLC') accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.


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