The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Oct. 23, 2015
Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Takeshi Furusawa, Ogaki, JP;

Kota Noda, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 1/09 (2006.01); H05K 3/46 (2006.01); H01L 23/13 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4697 (2013.01); H01L 21/486 (2013.01); H01L 23/13 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H05K 1/18 (2013.01); H05K 1/183 (2013.01); H05K 3/0097 (2013.01); H05K 3/4602 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/107 (2013.01);
Abstract

A printed wiring board includes a substrate, a first conductor layer formed on first surface of the substrate, a second conductor layer formed on second surface of the substrate, a through-hole conductor penetrating through the substrate and connecting the first and second conductor layers, a build-up layer formed on the second surface of the substrate and including conductor layers, insulating layers and via conductors, and a first insulating layer formed on the first surface the substrate and covering the first conductor layer. The substrate has a cavity penetrating through the first insulating layer and substrate and exposing the build-up layer on the substrate, the via conductors include a lowermost via conductor having a bottom portion exposed at bottom of the cavity, and the bottom portion of the lowermost via conductor is recessed relative to surface of a lowermost insulating layer in the build-up layer at the bottom of the cavity.


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