The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Apr. 11, 2016
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Alexey Kudymov, Ringoes, NJ (US);

Linlin Liu, Hillsborough, NJ (US);

Xiaohui Wang, East Brunswick, NJ (US);

Jamal Ramdani, Lambertville, NJ (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/00 (2006.01); H01L 29/00 (2006.01); H01L 29/778 (2006.01); H01L 23/31 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 23/29 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 29/205 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/0217 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H01L 29/41775 (2013.01); H01L 29/517 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01);
Abstract

A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode.


Find Patent Forward Citations

Loading…