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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9721857 B1

PDFFull Text
Date of Patent:
Aug. 01, 2017

Filed:

Mar. 10, 2016

Semiconductor device and manufacturing method thereof

Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Yoshiki Yamamoto, Kanagawa, JP;

Tetsuya Yoshida, Kanagawa, JP;

Koetsu Sawai, Kanagawa, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Shaun Campbell

Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 27/12 (2006.01); H01L 21/768 (2006.01); H01L 27/11 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 21/76897 (2013.01); H01L 22/30 (2013.01); H01L 23/535 (2013.01); H01L 23/53266 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 27/1207 (2013.01); H01L 22/34 (2013.01); H01L 2924/0002 (2013.01);
Abstract

When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Find Patent Forward Citations

Yamamoto, Yoshiki. (2017). Semiconductor device and manufacturing method thereof (U.S. Patent No. 9721857). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9721857

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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