The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Dec. 30, 2011
Boris Ginzburg, Haifa, IL;
Ilya Osadchiy, Haifa, IL;
Ronny Ronen, Haifa, IL;
Eliezer Weissmann, Haifa, IL;
Michael Mishaeli, Zichron Yaakov, IL;
Alon Naveh, Ramat Hasharon, IL;
David A. Koufaty, Portland, OR (US);
Scott D. Hahn, Beaverton, OR (US);
Tong LI, Portland, OR (US);
Avi Mendleson, Haifa, IL;
Eugene Gorbatov, Portland, OR (US);
Hisham Abu-salah, Majdal Shams, IL;
Dheeraj R. Subbareddy, Hillsboro, OR (US);
Paolo Narvaez, Wayland, MA (US);
Aamer Jaleel, Hudson, MA (US);
Efraim Rotem, Haifa, IL;
Yuval Yosef, Hadera, IL;
Anil Aggarwal, Portland, OR (US);
Kenzo Van Craeynest, Waregem, BE;
Boris Ginzburg, Haifa, IL;
Ilya Osadchiy, Haifa, IL;
Ronny Ronen, Haifa, IL;
Eliezer Weissmann, Haifa, IL;
Michael Mishaeli, Zichron Yaakov, IL;
Alon Naveh, Ramat Hasharon, IL;
David A. Koufaty, Portland, OR (US);
Scott D. Hahn, Beaverton, OR (US);
Tong Li, Portland, OR (US);
Avi Mendleson, Haifa, IL;
Eugene Gorbatov, Portland, OR (US);
Hisham Abu-Salah, Majdal Shams, IL;
Dheeraj R. Subbareddy, Hillsboro, OR (US);
Paolo Narvaez, Wayland, MA (US);
Aamer Jaleel, Hudson, MA (US);
Efraim Rotem, Haifa, IL;
Yuval Yosef, Hadera, IL;
Anil Aggarwal, Portland, OR (US);
Kenzo Van Craeynest, Waregem, BE;
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.