The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Aug. 31, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yong-En Syu, Tainan, TW;

Kuan-Chi Tsai, Kaohsiung, TW;

Kuo-Yu Cheng, Tainan, TW;

Keng-Yu Chen, Tainan, TW;

Shih-Shiung Chen, Tainan, TW;

Shao-Yu Chen, Tainan, TW;

Wei-Kung Tsai, Tainan, TW;

Yu-Lung Yeh, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/11573 (2017.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/0649 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.


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