The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Oct. 19, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chih-Kai Cheng, Hsinchu County, TW;

Cheng-Chieh Hsieh, Tainan, TW;

Shih-Wen Huang, Chiayi County, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/7685 (2013.01); H01L 21/76816 (2013.01); H01L 21/76898 (2013.01); H01L 24/08 (2013.01); H01L 2224/0221 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/08054 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/32113 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/35121 (2013.01);
Abstract

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.


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