The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2017
Filed:
May. 18, 2015
Applicant:
Xintec Inc., Taoyuan, TW;
Inventors:
Assignee:
XINTEC INC., Taoyuan, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/033 (2006.01); H01L 21/302 (2006.01); H01L 23/48 (2006.01); H01L 21/268 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/0334 (2013.01); H01L 21/268 (2013.01); H01L 21/302 (2013.01); H01L 21/48 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/03 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/03831 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05557 (2013.01);
Abstract
A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.