The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2017
Filed:
Mar. 14, 2014
Applicant:
Yale University, New Haven, CT (US);
Inventors:
Assignee:
Yale University, New Haven, CT (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/02 (2006.01); C30B 25/04 (2006.01); C30B 29/40 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0254 (2013.01); C30B 25/04 (2013.01); C30B 29/406 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02422 (2013.01); H01L 21/02433 (2013.01); H01L 21/02458 (2013.01); H01L 21/02639 (2013.01); H01L 21/02647 (2013.01); H01L 23/49827 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.