The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Nov. 16, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Dean K. Nobunaga, Cupertino, CA (US);

Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US);

Xiaojiang Guo, San Jose, CA (US);

Eric N. Lee, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 11/00 (2006.01); G06F 3/06 (2006.01); G06F 12/0893 (2016.01); G11C 8/12 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G06F 12/0802 (2016.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G06F 12/0802 (2013.01); G06F 12/0893 (2013.01); G06F 13/1684 (2013.01); G06F 13/4068 (2013.01); G11C 5/066 (2013.01); G11C 7/1048 (2013.01); G11C 8/12 (2013.01); G11C 11/00 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/3042 (2013.01);
Abstract

Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.


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