The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Jan. 17, 2012
Applicants:

Duan Quan Liao, Singapore, SG;

Yikun Chen, Singapore, SG;

Ching-hwa Tey, Singapore, SG;

Xiao Zhong Zhu, Singapore, SG;

Inventors:

Duan Quan Liao, Singapore, SG;

Yikun Chen, Singapore, SG;

Ching-Hwa Tey, Singapore, SG;

Xiao Zhong Zhu, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/517 (2013.01);
Abstract

A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.


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