The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Dec. 04, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Masatoshi Nishikawa, Yokkaichi, JP;

Kota Funayama, Kuwana, JP;

Toru Miwa, Yokohama, JP;

Hiroyuki Ogawa, Nagoya, JP;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H01L 27/1157 (2017.01); H01L 27/11578 (2017.01); H01L 49/02 (2006.01); H01L 21/283 (2006.01); H01L 21/225 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/2253 (2013.01); H01L 21/283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11578 (2013.01); H01L 28/20 (2013.01);
Abstract

A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.


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