The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Feb. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert M. Nickerson, Chandler, AZ (US);

Min Tao, Chandler, AZ (US);

John S. Guzek, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 29/24 (2006.01); H01L 23/48 (2006.01); H01L 23/49 (2006.01); H05K 1/18 (2006.01); H01L 23/00 (2006.01); H05K 3/46 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 23/4985 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/20 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H05K 1/185 (2013.01); H05K 3/4682 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/16147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/821 (2013.01); H01L 2224/92224 (2013.01); H01L 2224/97 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H05K 1/186 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/1469 (2013.01);
Abstract

An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.


Find Patent Forward Citations

Nickerson, Robert. (2017). Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility (U.S. Patent No. 9691728). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9691728

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…