The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Sep. 05, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Guan Huei See, Singapore, SG;

Rui Tze Toh, Singapore, SG;

Shaoqiang Zhang, Singapore, SG;

Purakh Raj Verma, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/308 (2006.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76229 (2013.01); H01L 21/265 (2013.01); H01L 21/3083 (2013.01); H01L 21/76237 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01); H01L 23/485 (2013.01);
Abstract

Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer. The body contact region includes a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures.


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