The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Sep. 09, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Reza A. Pagaila, Tangerang, ID;

Byung Tai Do, Singapore, SG;

Linda Pei Ee Chua, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 23/315 (2013.01); H01L 25/00 (2013.01); H01L 25/0657 (2013.01); H01L 21/563 (2013.01); H01L 23/66 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.


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