The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jun. 17, 2015
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Ming-Tzong Yang, Baoshan Township, Hsinchu County, TW;

Wei-Che Huang, Zhudong Township, Hsinchu County, TW;

Tzu-Hung Lin, Zhubei, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/3171 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/18162 (2013.01);
Abstract

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.


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