The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2017
Filed:
Mar. 20, 2014
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); G06F 2217/84 (2013.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.
Chuang, Yi-Lin. (2017). Method for layout design and structure with inter-layer vias (U.S. Patent No. 9679840). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9679840
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile