The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jun. 30, 2016
Applicant:

Stats Chippac Pte. Ltd., Singapore, SG;

Inventors:

Zigmund Ramirez Camacho, Singapore, SG;

Bartholomew Liao Chung Foh, Singapore, SG;

Sheila Marie L. Alvarez, Singapore, SG;

Dao Nguyen Phu Cuong, Singapore, SG;

HeeJo Chi, Yeoju-gun, KR;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01); H01L 23/485 (2006.01); H01L 21/033 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0335 (2013.01); H01L 21/56 (2013.01); H01L 21/76879 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53233 (2013.01); H01L 23/53242 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/43 (2013.01); H01L 24/45 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05026 (2013.01);
Abstract

A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.


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