The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Mar. 12, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mikhail Smelyanskiy, San Francisco, CA (US);

Victor Lee, Santa Clara, CA (US);

Christopher Hughes, Santa Clara, CA (US);

Daehyun Kim, San Jose, CA (US);

Yen-Kuang Chen, Cupertino, CA (US);

Changkyu Kim, San Jose, CA (US);

Jatin Chhugani, Santa Clara, CA (US);

Anthony D. Nguyen, Castro Valley, CA (US);

Sanjeev Kumar, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 15/76 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06T 5/40 (2006.01); H04N 1/407 (2006.01); G06K 9/62 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 9/3004 (2013.01); G06F 9/30018 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30087 (2013.01); G06F 9/3834 (2013.01); G06F 9/3885 (2013.01); G06K 9/6212 (2013.01); G06T 5/40 (2013.01); H04N 1/4074 (2013.01);
Abstract

In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.


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