The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

May. 27, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Annie Levesque, Wappingers Falls, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Matthew W. Stoker, Poughskeepsie, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/665 (2013.01); H01L 21/28518 (2013.01); H01L 21/28525 (2013.01); H01L 21/823814 (2013.01); H01L 29/41783 (2013.01); H01L 29/6656 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01);
Abstract

A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.


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